This invention relates to structures and techniques for construction of solar cells based on III-V materials, such as gallium and arsenide. More particularly, this invention relates to the problem of forming reliable electrically conductive contacts for electrical terminals for devices or structures incorporating III-V materials.
Conventional or known III-V GaAs-based solar cells typically consist of multiple p-n junctions (sub-cells) connected in series with tunnel junctions. There are many III-V solar cell designs described in the literature. A schematic cross-sectional representation of a III-V solar cell 1 appears in FIG. 1. Most designs consist of a thin n-type emitter region on top of a thicker p-type base region (an “n-on-p” type structure), although the opposite configuration can also be employed (“p-on-n”). The designs may also include back and front surface fields around a p-n junction, in addition to tunnel junctions connecting various p-n junctions. It should be understood that within a tunnel junction are complex functional structures that are not fully described herein but which are understood by those of skill in the art.
The III-V solar cell device 1 can be divided into three parts—a lower region 10, a middle region 20, and an upper region 30, as shown in FIG. 2. The lower region 10 is a substrate on which the device layers adhere. In addition, the lower region 10 may incorporate a back or bottom contact to the substrate. The middle region 20 contains heteroepitaxial III-V device layers. The middle region 20 forms at least one p-n junction, which may either be completely contained within the middle region 20, or it may be formed between the substrate 10 and the middle region 20. In a specific proprietary embodiment, these device layers may comprise at least one dilute nitride n-on-p sub-cell. The upper region 30 may comprise the semiconductor and metal layers required to make electrical contact for the device 1, in addition to the anti-reflection coating (ARC) layers to promote solar energy absorption. (In most of the figures in this disclosure, the ARC layers are omitted for simplicity of illustration. It should be understood that such layers are present.) FIG. 1 thus shows how a typical ARC integrates into a solar cell device.
Generally, the metal layers in the upper region 30 are patterned into a grid of lines 40, as shown in FIG. 3. The metal stack used for the grid must be sufficiently thick to conduct the solar-generated current produced by the cell with little resistance. Metal stack thicknesses on the order of 5 μm containing mostly silver or gold are known.
In some solar cells, the top grid metallization generally makes electrical contact to an n-GaAs contact layer 31. (See FIG. 4).